1. Field of the Invention
The present invention relates to a DC-DC converter for generating a constant voltage, and more particularly, to a DC-DC converter circuit provided with a soft start function.
2. Description of the Related Art
As a conventional DC-DC converter provided with a soft start function, a configuration illustrated in FIG. 6 is known. FIG. 6 illustrates a buck DC-DC converter by way of example.
A reference voltage circuit 103 is connected to a bias circuit 134 and a drain of a transistor 132. The transistor 132 has a gate connected to a connection point between a bias circuit (constant current circuit) 131 and a capacitor 133, and a source connected to a bias circuit 135 and a non-inverting input terminal of an error amplifier 101 as a node Vref_ss. The error amplifier 101 has an inverting input terminal connected to an FB terminal 120, and an output connected to a non-inverting input terminal of a pulse width modulation (PWM) comparator 102. The PWM comparator 102 has an inverting input terminal connected to a triangular wave generator circuit 104, and an output connected to an input terminal of a buffer 107. The buffer 107 has an output terminal connected to an EXT terminal 121. An external N-channel field-effect transistor (FET) 114 has a gate connected to the EXT terminal 121, a drain connected to an inductor 112 and an anode of a diode 113, and a source connected to a ground 123. On the opposite side of the inductor 112, a power supply terminal 110 and a capacitor 111 are connected in parallel. The diode 113 has a cathode connected to a capacitor 115 and an output terminal 122. The output terminal 122 is connected in parallel to a resistor 117 and a capacitor 116. A resistor 118 is connected to the resistor 117, and a connection point between the resistor 118 and the resistor 117 is connected to the FB terminal 120.
When a power supply voltage is supplied between the power supply terminal 110 and the ground 123, a current flows from the bias circuit 131 so that charges are stored into the capacitor 133 to increase a gate voltage of the transistor 132 gradually. In this way, the transistor 132 gradually approaches an ON state, and the node Vref_ss gradually increases to a reference voltage. As the voltage of the non-inverting input terminal of the error amplifier 101 increases gradually, the output of the error amplifier 101 also increases gradually. Accordingly, the PWM comparator 102 compares the gradually-increasing output of the error amplifier 101 with an output of the triangular wave generator circuit 104, to thereby output a gradually-thickening duty pulse with respect to a thin duty pulse. The pulse is supplied to the gate of the external N-channel FET 114 via the buffer 107 to control an output voltage to increase gradually. Because the output voltage is controlled to increase gradually, an overshoot or an inrush current may be prevented from occurring (see, for example, Japanese Patent Application Laid-open No. 2005-51956).
In order to suppress an inrush current flowing into the FET, a soft start circuit is required to provide a soft start time of several milliseconds. The conventional circuit raises the node Vref_ss gradually, and hence the node needs to spend several milliseconds being raised. Therefore, on the condition that the output of the soft start circuit should be raised to a voltage Vref (for example, 0.6 V) after several milliseconds, a capacitance of approximately 100 pF is necessary when a current of the constant current circuit 131 is 20 nA.
In order to further prolong the soft start time, the capacitance needs to be increased. However, this is difficult to realize in terms of an increase in chip size. On the other hand, it is conceivable to reduce the constant current value to prolong the soft start time with the same capacitance. However, when the constant current value is set to a microcurrent of approximately 10 nA or smaller, an amount of a leakage current becomes non-negligible under high temperature, leading to a malfunction of the soft start circuit. For that reason, there is a limitation to prolong the soft start time by reducing the constant current value with the capacitance unvaried, avoiding the change in chip size. In terms of practical use, it is reasonable that the constant current value be approximately 20 nA and the capacitance be approximately 100 pF.